System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
< data not available > < data not available > < data not available >
Path D:\Xilinx\12.2\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\12.2\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.2\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.2\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.2\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.2\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.2\ISE_DS\common\bin\nt64;
D:\Xilinx\12.2\ISE_DS\common\lib\nt64;
c:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
D:\Program Files\Autodesk\Backburner\;
C:\Program Files (x86)\Common Files\Autodesk Shared\;
D:\Program Files\TortoiseSVN\bin;
C:\Windows\SUA\common\;
C:\Windows\SUA\usr\lib\;
D:\Program Files (x86)\Microchip\MPLAB IDE\VDI;
d:\Program Files (x86)\HI-TECH Software\PICC\9.70\bin;
D:\Program Files (x86)\Altium Designer Summer 09\System;
d:\MCC18\mpasm;
d:\MCC18\bin;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Satsuki Decoder Pack\Filtres;
d:\Program Files (x86)\gputils\bin
< data not available > < data not available > < data not available >
XILINX D:\Xilinx\12.2\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP D:\Xilinx\12.2\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK D:\Xilinx\12.2\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD D:\Xilinx\12.2\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   LCD6100_Epson_driver.prj  
-ifmt   mixed MIXED
-ofn   LCD6100_Epson_driver  
-ofmt   NGC NGC
-p   xc3s400a-4-ft256  
-top   LCD6100_Epson_driver  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   24 24
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz/3528 MHz <  data not available  > <  data not available  > <  data not available  >
Host Perle <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft <  data not available  > <  data not available  > <  data not available  >
OS Release major release (build 7600) <  data not available  > <  data not available  > <  data not available  >